Field of the Invention
The invention is directed to a non-volatile semiconductor memory device (e.g., a flash memory) and a driving method for a word line thereof.
Description of Related Art
An NAND or an NOR flash memory requires a high voltage for a data reading, programming or erasing operation. Generally, in the flash memory, a low power supply voltage is supplied from the external, the supplied voltage is boosted by a charge pump, and a program voltage or an erase voltage is generated by the boosted voltage. If a word line decoder is provided with the charge pump, the size of the word line decoder is increased due to the area occupied by a capacitor. Thus, Japanese Patent Publication No. 2002-197882 discloses a word line decoder of which a layout area is reduced by omitting a charge pump. The word line decoder is self-boosted by a word line enablement signal used for enabling the word line, thereby suppressing the reduction of a word line driving voltage.
The reading or programming operation in the flash memory is usually performed by using a page as a unit. A word line selection circuit selects a block from a memory cell array by decoding a row address and selects a word line in the selected block. FIG. 1 illustrates a block selection operation of the word line selection circuit. A voltage Vpp boosted by a charge pump circuit 10 is supplied to a level shifter 20. The level shifter 20, in response to a decoding result of the row address (which is a block selection signal BLKSEL), outputs an output signal BDRV. The output signal BDRV of the level shifter 20 is commonly connected to a gate of a block selection transistor 30. The block selection transistor 30, in response to the output signal BDRV, supplies a voltage supplied by a voltage supplying element 40 to each word line (WL0 to WL31) and each selection gate line (SGD and SGS) of the selected block 50.
For example, during a programming operation, the voltage supplying element 40 supplies an intermediate voltage (e.g., 10 V) to each word line of the selected block, then, a program voltage (e.g., 25 V) to a selected word line, an intermediate voltage (e.g., 10 V) to a non-selected word line, a driving voltage (e.g., a Vcc voltage or 5 V, and so on) to the selection gate line SGD, and 0 V to the selection gate line SGS. Additionally, a potential corresponding to data “0” or “1” is supplied to a bit line GBL by a page buffer/read circuit. On the other hand, the level shifter 20, in the consideration of a voltage drop of a threshold of the block selection transistor 30 and a back gate bias effect from a source when the block selection transistor 30 is turned on, supplies an output signal BDRV with a voltage (e.g., 31 V) which is higher than the program voltage, so as to prevent the program voltage from decreasing. Thus, the charge pump circuit 10 has to generate a boost voltage Vpp of at least 31 V.
In order to generate a high voltage (e.g., 31 V) by the charge pump circuit 10, the number of stages of the charge pumps has to be increased. In particular, if the external power supplied to the memory chip is a low voltage, the number of stages has to be correspondingly increased. However, in case the number of stages of the charge pump circuit 10 is increased, boosting efficiency will be decreased. Therefore, issues of increased power consumption and an increased occupied area of the charge pump circuit 10 arise.